rev 2.1 ?2010 advanced linear devices, inc. 415 tasman drive, sunnyvale, ca 94089-1706 tel: (408) 747-1155 fax: (408) 747-1286 www.aldinc.com general description the ald1712a/ald1712b/ald1712 is a monolithic precision opera- tional amplifier intended primarily for a wide range of analog applications in +5v single power supply and 5v dual power supply systems as well as +5v to +10v battery operated systems. all device characteristics are specified for +5v single supply or 2.5v dual supply systems. it is manufactured with advanced linear devices' enhanced acmos silicon gate cmos process and is available as a standard cell in ald's asic "function-specific" library. the ald1712a/ald1712b/ald1712 has an input stage that operates to +300mv above and -300mv below the supply voltages with no adverse effects and/or phase reversals. it has been developed specifically with the 5v single supply or 2.5v dual supply user in mind. several important characteristics of the device make many applications easy to implement for these supply voltages. first, the operational amplifier can operate with rail-to-rail input and output voltages. this feature allows numerous analog serial stages to be implemented without losing operating voltage margin. second, the device was designed to accommodate mixed applications where digital and analog circuits may work off the same 5v power supply. third, the output stage can drive up to 400pf capacitive, and 1k ? resistive loads in non-inverting unity gain connection, and up to 4000pf at a gain of 5. these features, coupled with extremely low input currents, high voltage gain, useful bandwidth of 1.5mhz, slew rate of 2.1v/ s, low power dissipation, low offset voltage and temperature drift, make the ald1712a/ald1712b/ald1712 a truly versatile, user friendly, operational amplifier. on-chip offset voltage trimming allows the device to be used without nulling in most applications. the device offers typical offset drift of less than 5 v/ c which eliminates many trim or temperature compensation circuits. for precision applications, the ald1712a/ald1712b/ald1712 is designed to settle to 0.01% in 8 s. the unique characteristics at input and output are modeled in an available macromodel. additionally, robust design and rigorous screening make this device especially suitable for operation in temperature-extreme environments and rugged conditions. rail-to-rail precision operational amplifier ald1712a/ald1712b ald1712 a dvanced l inear d evices, i nc. operating temperature range 0 c to +70 c0 c to +70 c -55 c to 125 c 8-pin 8-pin 8-pin small outline plastic dip cerdip package (soic) package package ald1712asal ald1712apal ald1712ada ald1712bsal ALD1712BPAL ald1712bda ald1712sal ald1712pal ald1712da * contact factory for leaded (non-rohs) or high temperature versions. ordering information (?l? suffix denotes lead-free (rohs)) features ? linear mode operation with input voltages 300mv beyond supply rails ? symmetrical complementary output drive ? output voltages to within 2mv of power supply rails ? high load capacitance capability -- 4000pf typical ? no frequency compensation required -- unity gain stable ? extremely low input bias currents -- 0.01pa typical ? dual power supply 2.5v to 5.0v ? single power supply +5v to +10v ? high voltage gain ? typically 85v/mv @ 2.5v and 250v/mv @ 5.0v ? drive as low as 1k ? load with 5ma drive current ? output short circuit protected ? unity gain bandwidth of 1.5mhz ? slew rate of 2.1v/ s ? suitable for rugged, temperature-extreme environments applications ? voltage amplifier ? voltage follower/buffer ? charge integrator ? photodiode amplifier ? data acquisition systems ? high performance portable instruments ? signal conditioning circuits ? sensor and transducer amplifiers ? low leakage amplifiers ? active filters ? sample/hold amplifier ? picoammeter ? current to voltage converter ? coaxial cable driver pin configuration * n/c pins are internally connected. do not connect externally. 1 2 2 3 4 8 7 6 5 n/c -in +in n/c out n/c v - v + top view sal, pal, da packages
ald1712a/ald1712b advanced linear devices 2 of 9 ald1712 absolute maximum ratings supply voltage, v + 10.6v differential input voltage range -0.3v to v + +0.3v power dissipation 600 mw operating temperature range sal, pal packages 0 c to +70 c da package -55 c to +125 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c caution: esd sensitive device. use static control procedures in esd controlled environment. supply v s 2.0 5.0 2.0 5.0 2.0 5.0 v dual supply voltage v + 4.0 10.0 4.0 10.0 4.0 10.0 v single supply input offset v os 0.05 0.15 0.1 0.25 0.25 0.5 mv r s 100k ? voltage 0.35 0.55 1.0 mv 0 c t a +70 c input offset i os 0.01 10 0.01 10 0.01 10 pa t a = 25 c current 280 280 280 pa 0 c t a +70 c input bias i b 0.01 10 0.01 10 0.01 10 pa t a = 25 c current 280 280 280 pa 0 c t a +70 c input voltage v ir -0.3 5.3 -0.3 5.3 -0.3 5.3 v v + = +5; notes 2,5 range -2.8 +2.8 -2.8 +2.8 -2.8 +2.8 v v s = 2.5v input r in 10 13 10 13 10 13 ? resistance input offset tcv os 555 v/ cr s 100k ? voltage drift power supply psrr 65 85 65 85 63 85 db r s 100k ? rejection ratio 65 85 65 85 63 85 db 0 c t a +70 c common mode cmrr 65 83 65 83 63 83 db r s 100k ? rejection ratio 65 83 65 83 63 83 db 0 c t a +70 c large signal a v 50 85 50 85 50 85 v/mv r l = 10k ? voltage gain 400 400 400 v/mv r l 1m ? 20 20 20 v/mv r l = 10k ? 0 c t a +70 c output v o low 0.002 0.01 0.002 0.01 0.002 0.01 v r l = 1m ? v + = +5v voltage v o high 4.99 4.998 4.99 4.998 4.99 4.998 v 0 c t a +70 c range v o low -2.44 -2.35 -2.44 -2.35 -2.44 -2.35 v r l = 10k ? v o high 2.35 2.44 2.35 2.44 2.35 2.44 v 0 c t a +70 c output short i sc 888ma circuit current supply i s 0.8 1.5 0.8 1.5 0.8 1.5 ma v in = 0v current no load power p d 4.0 7.5 4.0 7.5 4.0 7.5 mw v s = 2.5v dissipation input c in 111pf capacitance bandwidth b w 1.0 1.5 1.0 1.5 1.0 1.5 mhz slew rate s r 1.4 2.1 1.4 2.1 1.4 2.1 v/ sa v = +1 r l = 10k ? rise time t r 0.2 0.2 0.2 sr l = 10k ? overshoot 10 10 10 % r l = 10k ? factor c l = 100pf operating electrical characteristics t a = 25 c v s = 2.5v unless otherwise specified 1712a 1712b 1712 parameter symbol min typ max min typ max min typ max unit test conditions
ald1712a/ald1712b advanced linear devices 3 of 9 ald1712 operating electrical characteristics (cont'd) maximum load c l 400 400 400 pf gain = 1 capacitance 4000 4000 4000 pf gain = 5 input noise voltage e n 26 26 26 nv/ hz f =1khz input current noise i n 0.6 0.6 0.6 fa/ hz f =10hz settling t s 8.0 8.0 8.0 s 0.01% time 3.0 3.0 3.0 s 0.1% a v = -1 r l = 5k ? c l = 50pf t a = 25 c v s = 2.5v unless otherwise specified 1712a 1712b 1712 parameter symbol min typ max min typ max min typ max unit test conditions t a = 25 c v s = 5.0v unless otherwise specified 1712a 1712b 1712 parameter symbol min typ max min typ max min typ max unit test conditions power supply psrr 83 83 83 db r s 100k ? rejection ratio common mode cmrr 83 83 83 db r s 100k ? rejection ratio large signal a v 250 250 250 v/mv r l = 10k ? voltage gain output voltage v o low -4.90 -4.80 -4.90 -4.80 -4.90 -4.80 v r l = 10k ? range v o high 4.80 4.93 4.80 4.93 4.80 4.93 bandwidth b w 1.7 1.7 1.7 mhz slew rate s r 2.8 2.8 2.8 v/ sa v =+1 c l =50pf v s = 2.50v -55 c t a +125 c unless otherwise specified 1712ada 1712bda 1712da parameter symbol min typ max min typ max min typ max unit test conditions input offset v os 0.5 1.0 0.8 1.5 1.2 2.5 mv r s 100k ? voltage input offset i os 4.0 4.0 4.0 na current input bias i b 4.0 4.0 4.0 na current power supply psrr 60 83 60 83 60 83 db r s 100k ? rejection ratio common mode cmrr 60 83 60 83 60 83 db r s 100k ? rejection ratio large signal a v 10 25 10 25 10 25 v/mv r l = 10k ? voltage gain output voltage v o low 0.1 0.2 0.1 0.2 0.1 0.2 v r l 10k ? range v o high 4.8 4.9 4.8 4.9 4.8 4.9 v r l 10k ?
ald1712a/ald1712b advanced linear devices 4 of 9 ald1712 design & operating notes: 1. the ald1712a/ald1712b/ald1712 cmos operational amplifier uses a 3 gain stage architecture and an improved frequency compensation scheme to achieve large voltage gain, high output driving capability, and better frequency stability. in a conventional cmos operational amplifier design, compensation is achieved with a pole splitting capaci- tor together with a nulling resistor. this method is, however, very bias dependent and thus cannot accommodate the large range of supply voltage operation as is required from a stand alone cmos operational amplifier. the ald1712a/ald1712b/ald1712 is internally compen- sated for unity gain stability using a novel scheme that does not use a nulling resistor. this scheme produces a clean single pole roll off in the gain characteristics while providing for more than 70 degrees of phase margin at the unity gain frequency. a unity gain buffer using the ald1712a/ald1712b/ald1712 will typically drive 400pf of external load capacitance without stability problems. in the inverting unity gain configuration, it can drive up to 800pf of load capacitance. compared to other cmos operational amplifiers, the ald1712a/ald1712b/ ald1712 has shown itself to be more resistant to parasitic oscillations. 2. the ald1712a/ald1712b/ald1712 has complementary p-channel and n-channel input differential stages connected in parallel to accom- plish rail to rail input common mode voltage range. this means that with the ranges of common mode input voltage close to the power supplies, one of the two differential stages is switched off internally. to maintain compatibility with other operational amplifiers, this switching point has been selected to be about 1.5v above the negative supply voltage. since offset voltage trimming on the ald1712a/ald1712b/ald1712 is made when the input voltage is symmetrical to the supply voltages, this internal switching does not affect a large variety of applications such as an inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5v operation), where the common mode voltage does not make excursions below this switching point. the user should however, be aware that this switching does take place if the operational amplifier is connected as a unity gain buffer and should make provision in his design to allow for input offset voltage variations. 3. the input bias and offset currents are essentially input protection diode reverse bias leakage currents, and are typically less than 1pa at room temperature. this low input bias current assures that the analog signal from the source will not be distorted by input bias currents. normally, this extremely high input impedance of greater than 10 12 ? would not be a problem as the source impedance would limit the node impedance. however, for applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 4. the output stage consists of class ab complementary output drivers, capable of driving a low resistance load. the output voltage swing is limited by the drain to source on-resistance of the output transistors as determined by the bias circuitry, and the value of the load resistor. when connected in the voltage follower configuration, the oscillation resistant feature, combined with the rail to rail input and output feature, makes an effective analog signal buffer for medium to high source impedance sensors, transducers, and other circuit networks. 5. the ald1712a/ald1712b/ald1712 operational amplifier has been designed to provide full static discharge protection. internally, the design has been carefully implemented to minimize latch up. however, care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. in using the operational amplifier, the user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages to not exceed 0.3v of the power supply voltage levels. typical performance characteristics input bias current as a function of ambient temperature ambient temperature ( c) 100 10 1.0 0.01 0.1 input bias current (pa) 100 -25 0 75 125 50 25 -50 1000 v s = 2.5v common mode input voltage range as a function of supply voltage supply voltage (v) common mode input voltage range (v) 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 t a = 25 c open loop voltage gain as a function of supply voltage and temperature supply voltage (v) 1000 100 10 1 open loop voltage gain (v/mv) 0 2 4 6 r l = 10k ? r l = 5k ? } -55 c } +25 c } +125 c 8 supply current as a function of supply voltage supply voltage (v) 5 4 2 3 0 1 supply current (ma) 0 1 2 3 4 5 6 -25 c +25 c +80 c +125 c inputs grounded output unloaded t a = -55oc
ald1712a/ald1712b advanced linear devices 5 of 9 ald1712 typical performance characteristics (cont'd) open loop voltage gain as a function of frequency frequency (hz) 1 10 100 1k 10k 1m 10m 100k 120 100 80 60 40 20 0 -20 open loop voltage gain (db) v s = 2.5v t a = 25 c 90 0 45 180 135 phase shift in degrees open loop voltage gain as a function of load resistance load resistance ( ? ) 1k 10k 1000k 100k 1000 100 10 1 open loop voltage gain (v/mv) v s = 2.5v t a = 25 c large - signal transient response 5v/div 1v/div 2 s/div v s = 2.5v t a = 25 c r l = 10k ? c l = 50pf small - signal transient response 100mv/div 20mv/div v s = 2.5v t a = 25 c r l = 10k ? c l = 50pf 2 s/div input offset voltage as a function of common mode input voltage common mode input voltage (v) -2 -1 0 +1 +2 +3 6 4 2 0 -2 -4 -6 input offset voltage (mv) v s = 2.5v t a = 25 c voltage noise density as a function of frequency frequency (hz) 10 100 1k 10k 100k 150 125 100 75 50 25 0 1000k voltage noise density (nv/ hz) v s = 2.5v t a = 25 c input offset voltage as a function of ambient temperature representative units ambient temperature ( c) input offset voltage (mv) -50 -25 0 +25 +50 +75 +100 +125 +4 +5 +3 +1 +2 0 -2 -1 -4 -3 -5 v s = 2.5v r l = 10k ? output voltage swing as a function of supply voltage supply voltage (v) output voltage swing (v) 3 0 1 2 3 4 5 6 7 r l = 2k ? 6 5 4 2 7 -55 c t a 125 c r l = 10k ?
ald1712a/ald1712b advanced linear devices 6 of 9 ald1712 typical applications ultra long time constant integrator wien bridge oscillator (rail-to-rail) sine wave generator low offset summing amplifier rail-to-rail voltage follower/buffer - + output v in 5v c l r l =10k ? 0.1 f ~ z in = 10 12 ? 400pf * see rail to rail waveform 0 v in 5v 10k - + output 10k 10k +2.5v -2.5v .01 f 1 2 r c f = ~ 1.6khz c = .01 f r = 10k * see rail to rail waveform ~ output input 1 input 2 - + +2.5v .01 f .01 f - 2.5v gain = 5 c l = 4000pf * circuit drives large load capacitance 4000pf 10k 10k 50k rail-to-rail waveform performance waveforms. upper trace is the output of a wien bridge oscillator. lower trace is the output of rail-to-rail voltage follower. 0v +5v output 0v +5v input - + 20k 20k relay 1 integrator voltage preset relay 2 r v in 3 2 4 0.1 -5 v 6 +5v 7 0.1 v = 1/rc ald1712 control 1 - + 1 2 3 1.5v 1/2 ald2301 8 5v * low leakage capacitor e.g. teflon capacitor type k11b104ksw component research inc. ? all capacitance values are in f unless otherwise specified. ? relays 1 & 2 are of type 4705, gordos corporation. 5v c * t 2 t 1 v in = dt control 2 - + 7 6 5 1.5v 1/2 ald2301 4 5v photo detector current to voltage converter + - +2.5v -2.5v r f = 5m r l = 10k v out = i x r f i photodiode rail-to-rail voltage comparator - + output 50k 0.1 f +5v 10m v in +5v
ald1712a/ald1712b advanced linear devices 7 of 9 ald1712 8 pin plastic soic package soic-8 package drawing millimeters inches min max min max dim a a 1 b c d-8 e e h l s 1.75 0.25 0.45 0.25 5.00 4.05 6.30 0.937 8 0.50 0.053 0.004 0.014 0.007 0.185 0.140 0.224 0.024 0 0.010 0.069 0.010 0.018 0.010 0.196 0.160 0.248 0.037 8 0.020 1.27 bsc 0.050 bsc 1.35 0.10 0.35 0.18 4.69 3.50 5.70 0.60 0 0.25 ? l c h s (45 ) ? e a a 1 b d s (45 ) e
ald1712a/ald1712b advanced linear devices 8 of 9 ald1712 8 pin plastic dip package pdip-8 package drawing b 1 s b e e 1 d e a 2 a 1 a l c e 1 ? millimeters inches min max min max dim a a 1 a 2 b b 1 c d-8 e e 1 e e 1 l s-8 ? 3.81 0.38 1.27 0.89 0.38 0.20 9.40 5.59 7.62 2.29 7.37 2.79 1.02 0 5.08 1.27 2.03 1.65 0.51 0.30 11.68 7.11 8.26 2.79 7.87 3.81 2.03 15 0.105 0.015 0.050 0.035 0.015 0.008 0.370 0.220 0.300 0.090 0.290 0.110 0.040 0 0.200 0.050 0.080 0.065 0.020 0.012 0.460 0.280 0.325 0.110 0.310 0.150 0.080 15
ald1712a/ald1712b advanced linear devices 9 of 9 ald1712 8 pin cerdip package cerdip-8 package drawing a a 1 b b 1 c d-8 e e 1 e e 1 l l 1 l 2 s ? 3.55 1.27 0.97 0.36 0.20 -- 5.59 7.73 3.81 3.18 0.38 -- 0 5.08 2.16 1.65 0.58 0.38 10.29 7.87 8.26 5.08 -- 1.78 2.49 15 millimeters inches min max min max dim 0.140 0.050 0.038 0.014 0.008 -- 0.220 0.290 0.150 0.125 0.015 -- 0 0.200 0.085 0.065 0.023 0.015 0.405 0.310 0.325 0.200 -- 0.070 0.098 15 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc e e 1 c e 1 ? s b l d b 1 e a l 2 a 1 l 1
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